An important consideration in integrated circuit design is conserving power in the manufactured IC. An integrated circuit may use more than one power supply voltage and may use more than one technique for power optimization. A power intent specification for an electronic circuit design often is provided that complies with a well recognized power intent specification format, such as the Common Power Format (CPF) or the Unified Power Format (UPF, e.g., both the Accellera UPF1.0 and IEEE 1801 aka UPF2.0) standards, for example. In general, a power intent specification is captured in one or more files and associated with a behavioral model of the design function, a manually created or synthesized design netlist in Verilog or VHDL format, or a manually created custom or an automatic place and route created design netlist in Verilog or VHDL format. The power intent specification describes power management constraints that are to be applied to the circuit design. A power intent specification will create power domains. A power intent specification also may specify voltage level shifting, driver or receiver isolation, power or ground switching, and state retention insertion constraints that are required for the low power function and can define existing low power features or features to be implemented during synthesis or place and route.
Testing an integrated circuit design that has or is specified to have power management circuitry specified in a power intent specification ordinarily involves determining whether power management constraints have been applied properly to the circuit design. Often, such testing involves determining whether power management constraints or power management circuit components specified by such constraints have been correctly applied or specified for application to signal paths within the circuit design. A typical integrated circuit design may include thousands or even millions of signal paths to which power management constraints are to be mapped. Testing and diagnosing issues on all paths can be a daunting challenge. There has been a need for an improved technique to test signal paths to which power management constraints have been mapped.